Senior Principal Design Engineer

Cadence

Bangalore, India
Systemverilog and uvm
Functional verification of pcie
Verification environments
We are hiring motivated and passionate Verification Engineers to join our PCIe Design IP group

Job Summary

  • We are hiring motivated and passionate Verification Engineers to join our PCIe Design IP group.
  • Key Responsibilities include verifying PCIe Design IP across multiple generations and developing SystemVerilog/UVM-based verification environments.
  • We’re doing work that matters. Help us solve what others can’t.

Matching Summary

We are hiring motivated and passionate Verification Engineers to join our PCIe Design IP group.

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • functional verification of PCIe
  • verification environments

Nice-to-have

  • motivated and passionate engineers
  • work that matters
  • solve what others can't

Key Requirements

  • 7 to 15 Years experience
  • Strong hands-on experience
  • Solid background in functional verification
  • Good understanding of verification methodologies

Work Rights

Not specified

Tailored Resume

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