Lead the development and optimization of standard cell libraries to enable best-in-class IP and product design on all generations of Intel technology
Job Summary
Lead the development and optimization of standard cell libraries to enable best-in-class IP and product design on all generations of Intel technology.
Manage a team responsible for circuit design, layout, extraction, characterization, modeling, reliability, and validation of standard cell libraries.
Collaborate with process technologists, product design, IFS stakeholders, and EDA vendors to achieve best-in-class PPA and competitive EoU through DTCO.
Matching Summary
Lead the development and optimization of standard cell libraries to enable best-in-class IP and product design on all generations of Intel technology.
Skills & Requirements
Must-have
Standard cell library development
Circuit design and layout
Extraction and characterization
FE/BE modeling and reliability
Process and PDK development
DTCO for PPA optimization
Nice-to-have
Foundry ecosystem and benchmarking
FINFET technologies and variation analysis
Scripting in TCL/PERL/Python
Cross-functional collaboration skills
Customer-oriented and analytical skills
Key Requirements
12+ years of experience in standard cell library domains
Deep working knowledge of digital logic design
Ability to manage diverse assignments and work under pressure