Senior Asic Verification Engineer

HPE (Hewlett Packard Enterprise)

Durham, United States
Base: 135,000 - 310,500 usd in north carolina; bon...
Hybrid
Systemverilog and uvm
Constrained-random tests
Coverage-driven methodologies
This role involves creating testbenches using SystemVerilog and UVM, building high-quality verification environments, writing directed and constrained-random tests, debugging failures, and working closely with architecture, design, and emulation teams

Job Summary

  • This role involves creating testbenches using SystemVerilog and UVM, building high-quality verification environments, writing directed and constrained-random tests, debugging failures, and working closely with architecture, design, and emulation teams.
  • The role also includes developing high-performance C++/SystemC reference models and participating in emulation and post-silicon validation.
  • We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Matching Summary

This role involves creating testbenches using SystemVerilog and UVM, building high-quality verification environments, writing directed and constrained-random tests, debugging failures, and working closely with architecture, design, and emulation teams.

Salary

Base: 135,000 - 310,500 USD in North Carolina; Bonus/Equity: Variable incentives may also be offered; Benefits: Comprehensive suite of benefits

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • constrained-random tests
  • coverage-driven methodologies
  • C++ and SystemC reference models
  • emulation environments
  • networking ASICs verification

Nice-to-have

  • growth mindset
  • intellectual curiosity
  • teamwork skills
  • problem-solving skills
  • flexibility to manage work

Key Requirements

  • 8+ years of experience
  • Bachelor's, Master's, or PhD
  • Work authorization for United States
  • Hybrid work model

Work Rights

Not specified

Tailored Resume

Cover Letter