Not specified; not specified; competitive compensa...
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Expert systemverilog and uvm knowledge
Deep mixed-signal design verification experience
Advanced debugging across rtl and gate-level
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Analog Devices is seeking a Staff Engineer for Soc Design Verification, responsible for leading verification strategies for complex analog and mixed-signal designs. The ideal candidate will possess extensive technical expertise, particularly in SystemVerilog and UVM, and will play a pivotal role in mentoring junior engineers and collaborating across teams.
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Job Summary
This senior position involves providing technical leadership in developing verification strategies for the company's most complex analog and mixed-signal designs.
The role requires mentoring junior engineers, coordinating cross-functional work, and serving as a principal customer contact to represent ADI's technical excellence.
Candidates will drive functional and code coverage closure while leading post-silicon validation activities to ensure product quality and reliability.
Matching Summary
Match Score: 75
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Analog Devices is seeking a Staff Engineer for Soc Design Verification, responsible for leading verification strategies for complex analog and mixed-signal designs. The ideal candidate will possess extensive technical expertise, particularly in SystemVerilog and UVM, and will play a pivotal role in mentoring junior engineers and collaborating across teams.
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Salary
Not specified; Not specified; Competitive compensation and benefits mentioned
Skills & Requirements
Must-have
Expert SystemVerilog and UVM knowledge
Deep mixed-signal design verification experience
Advanced debugging across RTL and gate-level
Proficiency with Cadence or Synopsys EDA tools
Strong Python, Perl, TCL, or Shell scripting skills