Mixed Signal Logic Design Engineer

Intel Corporation

Penang, Malaysia
Hybrid
Rtl coding and simulation for ddrphy ip
Define power intent strategy
Systemverilog rtl implementation
Develops the logic design, register transfer level (RTL) coding, and simulation for DDRPHY IP

Job Summary

  • Develops the logic design, register transfer level (RTL) coding, and simulation for DDRPHY IP.
  • Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
  • Follows secure development practices to address the security threat model and security objects within the design.

Matching Summary

Develops the logic design, register transfer level (RTL) coding, and simulation for DDRPHY IP.

Skills & Requirements

Must-have

  • RTL coding and simulation for DDRPHY IP
  • Define power intent strategy
  • SystemVerilog RTL implementation
  • Logic design integrity checks
  • Secure development practices

Nice-to-have

  • Coaching and training team members
  • Effort estimations and resource planning
  • Cross-site partner communication

Key Requirements

  • 8+ years RTL coding/IP integration
  • IP/Subsystem architecture knowledge
  • High-speed bus protocols (JEDEC)
  • Analog circuit integration knowledge
  • SystemVerilog, Lint, Synthesis, STA

Work Rights

Not specified

Tailored Resume

Cover Letter