Senior Hardware Asic Arch/design Engineer

NXP USA INC.

Ai inference chip architecture
Rtl implementation review
Ppa analysis and trade-offs
The role involves defining product features and owning the architecture for compute, memory, and high-speed interfaces in AI inference chips

Job Summary

  • The role involves defining product features and owning the architecture for compute, memory, and high-speed interfaces in AI inference chips.
  • Candidates will collaborate with software teams to co-optimize hardware features specifically for real-world AI workloads.
  • The position requires leading PPA analysis and guiding RTL implementation to ensure consistency with architectural intent and timing goals.

Matching Summary

The role involves defining product features and owning the architecture for compute, memory, and high-speed interfaces in AI inference chips.

Skills & Requirements

Must-have

  • AI inference chip architecture
  • RTL implementation review
  • PPA analysis and trade-offs
  • High-speed interface subsystems
  • Hardware-software co-design

Nice-to-have

  • Quantization and sparsity knowledge
  • Dataflow optimization skills
  • Debuggability and scalability focus
  • Memory bandwidth bottleneck analysis

Key Requirements

  • Strong understanding of AI inference workloads
  • Experience with quantization and dataflow
  • Knowledge of memory bandwidth bottlenecks

Work Rights

Not specified

Tailored Resume

Cover Letter