Pll Circuit Design Engineer

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On-site
Analog pll design
All digital pll design
Tsmc advanced process node
Design analog or all-digital PLLs at TSMC advanced process nodes using a mixed-mode design flow

Job Summary

  • Design analog or all-digital PLLs at TSMC advanced process nodes using a mixed-mode design flow.
  • Model PLLs using basic theory and Matlab codes, with familiarity in Spread-Spectrum-Clocks.
  • The company seeks proactive, self-motivated individuals with strong project management and communication skills.

Matching Summary

Design analog or all-digital PLLs at TSMC advanced process nodes using a mixed-mode design flow.

Skills & Requirements

Must-have

  • Analog PLL design
  • All digital PLL design
  • TSMC advanced process node
  • Mixed mode design flow
  • Device benchmark from PLL

Nice-to-have

  • Proactive and willing to take challenges
  • Highly self-motivated to learn
  • Strong project management
  • Effective communication skills
  • Organizing information

Key Requirements

  • Master degree in EE or higher
  • Minimum 5 years of working experience
  • Familiar with basic PLL theory
  • Familiar with Spread-Spectrum-Clocks
  • Designed analog or all-digital PLLs

Work Rights

Not specified

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