Our team is responsible for the physical implementation of Custom STD cells on industry-leading CMOS process nodes, enabling Cisco's next-generation networking devices
Job Summary
Our team is responsible for the physical implementation of Custom STD cells on industry-leading CMOS process nodes, enabling Cisco's next-generation networking devices.
You will work closely with circuit designers, CAD engineers, and verification teams to deliver robust, high-performance silicon in a highly collaborative environment.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.
Matching Summary
Our team is responsible for the physical implementation of Custom STD cells on industry-leading CMOS process nodes, enabling Cisco's next-generation networking devices.
Skills & Requirements
Must-have
Full Custom Layout Design
Cadence Virtuoso
Calibre DRC/LVS
IEEE standards
industry best practices
Nice-to-have
cross-functional collaboration
innovation
challenging the status quo
Key Requirements
5+ years' experience in Full Custom Layout Design
Electronics Practical Engineer certificate or Bachelor's degree