Serdes Ip Systems Engineering Director

Cadence Design Systems

San Jose, California, USA
Base: $178,500 to $331,500; bonus/equity: incentiv...
High speed serdes architecture
Communication systems fundamentals
Signal processing algorithms
This is a unique opportunity to join the rapidly growing Die-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems

Job Summary

  • This is a unique opportunity to join the rapidly growing Die-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems.
  • Main Job Tasks and Responsibilities: Key contributor and driver of the R&D team that defines, models and analyzes high performance D2D SerDes IP microarchitecture, link budget and specifications.
  • Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

Matching Summary

This is a unique opportunity to join the rapidly growing Die-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems.

Salary

Base: $178,500 to $331,500; Bonus/Equity: Incentive compensation (bonus, equity); Benefits: Paid vacation, 401(k) with match, ESPP, medical, dental, vision

Skills & Requirements

Must-have

  • high speed SerDes architecture
  • communication systems fundamentals
  • signal processing algorithms
  • systems simulation tools
  • group presentation and leadership skills

Nice-to-have

  • D2D link experience
  • emerging D2D standards
  • advanced technology nodes
  • 3D electromagnetic simulation tools

Key Requirements

  • PhD or M.S. in Electrical/Computer Engineering
  • 10+ years of experience with SerDes and PHYs
  • Strong mathematical skills
  • Strong coding skills
  • Good experimental skills
  • Experience generating systems or IBIS-AMI models
  • Demonstrated capacity to self-educate

Work Rights

Not specified

Tailored Resume

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