Candidate will be responsible for defining SoC level power delivery architecture and driving overall PDN convergence and Sign off for next generation Xeon Server SoC design
Job Summary
Candidate will be responsible for defining SoC level power delivery architecture and driving overall PDN convergence and Sign off for next generation Xeon Server SoC design.
Responsibilities include Block level/Full chip level EM/IR, PDN analysis, Signal EM and Power EM Signoff analysis, and ESD analysis and Signoff for High Performance complex SOCs.
The role involves validating IR Drops, working with SOC and Packaging Teams on design optimizations, and requires proficiency in scripting languages and PDN Signoff tools.
Matching Summary
Candidate will be responsible for defining SoC level power delivery architecture and driving overall PDN convergence and Sign off for next generation Xeon Server SoC design.
Skills & Requirements
Must-have
Block level/Full chip level EM/IR
PDN analysis and Signoff
Signal EM and Power EM Signoff
PG Grid spec development
ESD analysis and Signoff
Static IR, Dynamic IR Vless and VCD Checks
Perl, TCL Scripting Skills
Nice-to-have
Working with SOC and Packaging Teams
Good knowledge on PD
Effective communication with global teams
Key Requirements
Bachelors (B.Tech) or Masters (M.Tech) in Electrical Engineering
8+ years of experience in EM/IR, PDN analysis
Hands-on experience in PDN Signoff using Redhawk, RHSC, Voltus
Proficient in scripting languages (Tcl, Perl, Python)
Familiarity with Innovus for RDL and Bump Planning