Sr. Soc Design Verification Engineer

Altera

Bengaluru, Karnataka, India
Uvm methodology
System verilog language
Linux/unix scripting
As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology

Job Summary

  • As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology.
  • Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification.
  • Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan.

Matching Summary

As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology.

Skills & Requirements

Must-have

  • UVM methodology
  • System Verilog language
  • Linux/Unix scripting
  • Perl and/or Python proficiency
  • Design for Debug architecture verification

Nice-to-have

  • Emulation experience
  • ARM and RISC Debug Architectures
  • UltraSoC/Tessent Embedded Analytics Debug Architecture
  • working with geographically distributed teams

Key Requirements

  • 10+ years of experience with complex ASIC designs and/or verification
  • Experience on UVM verification methodology
  • Experience with formal verification method
  • Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same

Work Rights

Not specified

Tailored Resume

Cover Letter