Asic Verification Engineer - Acacia (hybrid)

Cisco UK

Maynard, MA, USA
Base: $148,800.00 - $212,900.00 (us/canada); bonus...
Hybrid
Systemverilog/uvm
C++
Asic verification methodologies
The ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent optical communications products

Job Summary

  • The ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent optical communications products.
  • This role requires someone to demonstrate their experience applying sophisticated verification techniques to ASIC projects, ensuring design quality, leading sophisticated technical projects, developing process improvements for the team, and mentoring teammates.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

The ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent optical communications products.

Salary

Base: $148,800.00 - $212,900.00 (US/Canada); Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k), paid parental leave, disability, life insurance, stock units, paid time off

Skills & Requirements

Must-have

  • SystemVerilog/UVM
  • C++
  • ASIC verification methodologies
  • verification test benches
  • test plans

Nice-to-have

  • track record of innovation
  • in house IP development
  • DSP algorithms
  • lab silicon validation
  • formal verification methodologies

Key Requirements

  • Bachelors + 8 years experience
  • Masters + 6 years experience
  • PhD + 3 years experience
  • Object-oriented verification methodologies

Work Rights

Not specified

Tailored Resume

Cover Letter