Full Chip Timing Modeling And Integration Engineer
Altera Digital Health
Penang, Malaysia
Static timing analysis (sta)
Liberty verilog sdc formats
Soc development experience
The role involves developing timing methodologies and executing full-chip timing for next-generation FPGA products in advanced process technologies
Job Summary
The role involves developing timing methodologies and executing full-chip timing for next-generation FPGA products in advanced process technologies.
Candidates will collaborate with cross-functional teams to define timing modeling strategies, generate high-level models, and validate them against design requirements.
This position requires solving critical design issues and driving continuous improvement within a fast-paced, dynamic engineering environment.
Matching Summary
The role involves developing timing methodologies and executing full-chip timing for next-generation FPGA products in advanced process technologies.
Skills & Requirements
Must-have
Static Timing Analysis (STA)
Liberty Verilog SDC formats
SoC development experience
Advanced process node knowledge
Python and Tcl scripting
Nice-to-have
Multi-voltage domain experience
FPGA DDR PCIe architecture
DFT constraint management
Cross-functional negotiation skills
Key Requirements
BS/MS Degree in Electrical or Computer Engineering
5+ years of relevant SoC development experience
Experience with AOCV and POCV silicon modeling concepts