Asic Engineer

Jane Street

New York, United States
On-site
4+ years practical experience in rtl design
Experience with synopsys or cadence flows
Front-end rtl design and synthesis skills
The role involves designing, testing, and deploying advanced hardware designs as part of the Ultra Low Latency team

Job Summary

  • The role involves designing, testing, and deploying advanced hardware designs as part of the Ultra Low Latency team.
  • Candidates will collaborate with professionals across trading, networking, and research infrastructure areas.
  • The company utilizes Hardcaml, a custom hardware development toolchain embedded in OCaml, to improve productivity.

Matching Summary

The role involves designing, testing, and deploying advanced hardware designs as part of the Ultra Low Latency team.

Skills & Requirements

Must-have

  • 4+ years practical experience in RTL design
  • Experience with Synopsys or Cadence flows
  • Front-end RTL design and synthesis skills
  • Back-end physical design expertise
  • Verification including formal methods
  • Programming in Python C++ Java or Haskell

Nice-to-have

  • Excitement about better engineering tools
  • Willingness to learn OCaml language
  • Collaboration across trading and research teams
  • Interest in software engineering techniques for hardware

Key Requirements

  • 4+ years practical experience in RTL design
  • Experience with ASIC design flows (Synopsys/Cadence)
  • Proficiency in high-level programming languages

Work Rights

Not specified

Tailored Resume

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