Principal Ams Verification Engineer (m/f/d)

NXP Semiconductors

France
**
Complex soc verification
Verification plan quality
Chip-level ams verification
** NXP Semiconductors is seeking a Principal AMS Verification Engineer to join their Secure Connected Edge team in France. The role involves complex SoC verification, requiring extensive experience in chip-level AMS verification, and offers competitive benefits, including a permanent contract and professional development opportunities. **

Job Summary

  • Work with the global design teams to do complex SOC verification for digital/analog/FW design.
  • Be responsible for verification plan quality, verification result/design target cross-check, test case development to reach better coverage and verification quality.
  • Besides a competitive salary, you will be eligible for our bonus plan and receive lunch vouchers, a higher than average number of vacation days and the possibility to buy company shares with a 15% discount.

Matching Summary

Match Score: 75

** NXP Semiconductors is seeking a Principal AMS Verification Engineer to join their Secure Connected Edge team in France. The role involves complex SoC verification, requiring extensive experience in chip-level AMS verification, and offers competitive benefits, including a permanent contract and professional development opportunities. **

Skills & Requirements

Must-have

  • complex SOC verification
  • verification plan quality
  • Chip-Level AMS Verification
  • Cadence AMS suite
  • C/C++, Bash, Python, Verilog/VerilogAMS, System-Verilog, Tcl, WREAL

Nice-to-have

  • drive diverse tasks involving several stakeholders
  • work independently
  • self-driven mentality
  • Synopsys VCS Mx
  • Cadence Virtuoso/Spectre, vManager, vPlan
  • revision control software

Key Requirements

  • 5+ years hands-on experience
  • Chip-Level AMS Verification on medium-complex designs
  • knowledge about: writing an exhaustive Top-Level AMS verification plan
  • setting-up an AMS flow
  • harmonizing it to the Digital Verification flow
  • techniques for minimizing simulation time and maximizing coverage
  • Knowledge of the Analog and Digital Design Flows
  • hands-on experience on at least one of the two

Work Rights

Not specified

Tailored Resume

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