Senior Asic Physical Design Engineer, Netlisting

Nvidia Corporation

Base: $136,000 - $218,500 usd (level 3); base: $16...
Logic equivalence checking from rtl to tapeout
Clock domain crossing checks and mtbf analysis
Full-chip static timing analysis (sta)
The role involves driving physical design of high-frequency and low-power CPUs, GPUs, and SoCs with a specific focus on netlist-related aspects

Job Summary

  • The role involves driving physical design of high-frequency and low-power CPUs, GPUs, and SoCs with a specific focus on netlist-related aspects.
  • Candidates must possess deep understanding of hardware architecture and hands-on skills in RTL/logic design for achieving timing closure.
  • NVIDIA offers competitive base salaries ranging from $136,000 to $264,500 depending on level, along with equity and benefits.

Matching Summary

The role involves driving physical design of high-frequency and low-power CPUs, GPUs, and SoCs with a specific focus on netlist-related aspects.

Salary

Base: $136,000 - $218,500 USD (Level 3); Base: $168,000 - $264,500 USD (Level 4); Equity and benefits included

Skills & Requirements

Must-have

  • Logic equivalence checking from RTL to tapeout
  • Clock domain crossing checks and MTBF analysis
  • Full-chip Static Timing Analysis (STA)
  • Timing constraints generation and management
  • ECO generation and implementation expertise
  • Perl, TCL, Make, Python scripting proficiency

Nice-to-have

  • Experience improving workflows via AI utilization
  • Strong hands-on debugging and problem-solving skills
  • DFT timing closure experience for scan shift modes
  • Background in flow development at project execution

Key Requirements

  • BS in Electrical/Computer Engineering with 5+ years experience
  • MS in Electrical/Computer Engineering with 3+ years experience
  • Expertise in industry-standard EDA tools for FV and synthesis

Work Rights

Not specified

Tailored Resume

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