Performs functional logic verification at multiple levels (block, subsystem and full chip) and defines and develops scalable and reusable verification plans, test benches, and the verification environment
Job Summary
Performs functional logic verification at multiple levels (block, subsystem and full chip) and defines and develops scalable and reusable verification plans, test benches, and the verification environment.
Executes verification plans, runs emulation and system simulation models, analyzes power and performance, and debugs issues in the pre-silicon environment.
Collaborates with Architects, microarchitects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Matching Summary
Performs functional logic verification at multiple levels (block, subsystem and full chip) and defines and develops scalable and reusable verification plans, test benches, and the verification environment.
Skills & Requirements
Must-have
functional logic verification
verification plans and test benches
System Verilog
constrained random verification
IP and/or SOC verification
security activities within test plans
Nice-to-have
learning from post-silicon
collaboration with cross-functional teams
improving verification infrastructure
Key Requirements
3-5+ years of technical experience
BS, MS or PhD in Electrical or Computer Science Engineering