Lead Cpu Design Engineer

Intel Corporation

Phoenix, Arizona, United States
Base: $164,470.00-232,190.00 usd; bonus/equity: st...
Hybrid
Cpu logic design
Rtl coding
Power, performance, area, timing goals
As a CPU Logic Design Engineer, you will play a pivotal role in designing and developing the logic architecture for CPUs that serve as the backbone of our cutting-edge technologies

Job Summary

  • As a CPU Logic Design Engineer, you will play a pivotal role in designing and developing the logic architecture for CPUs that serve as the backbone of our cutting-edge technologies.
  • Your contributions will directly impact Intel's ability to deliver high-performance, power-efficient processors that drive the future of computing.
  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

As a CPU Logic Design Engineer, you will play a pivotal role in designing and developing the logic architecture for CPUs that serve as the backbone of our cutting-edge technologies.

Salary

Base: $164,470.00-232,190.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • CPU logic design
  • RTL coding
  • power, performance, area, timing goals
  • microarchitecture development
  • debugging RTL implementation issues

Nice-to-have

  • strong communication skills
  • collaborative cross-functional teams
  • delivering high-quality designs
  • enthusiasm for innovation
  • understanding complex Intel Architecture CPU

Key Requirements

  • Bachelor's degree in EE, CE, or related field
  • 6+ years (BS), 4+ years (MS), or 2+ years (PhD) in CPU logic design, RTL coding, or microarchitecture
  • Experience with debugging and resolving RTL implementation issues
  • Experience with CPU architecture concepts
  • Experience developing and debugging functional tests in Assembly

Work Rights

Not specified

Tailored Resume

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