Mts Digital Verification Engineer

GlobalFoundries

Uvm-based verification environments
System verilog, uvm methodology
Constrained random verification
We are seeking a highly skilled Digital Verification Engineer to lead the verification strategy and execution for complex designs

Job Summary

  • We are seeking a highly skilled Digital Verification Engineer to lead the verification strategy and execution for complex designs.
  • This is a hands-on leadership role combining deep technical expertise with mentorship and cross-functional influence.
  • We Offer Base Salary Equity Annual Bonus Plan Medical Insurance

Matching Summary

We are seeking a highly skilled Digital Verification Engineer to lead the verification strategy and execution for complex designs.

Skills & Requirements

Must-have

  • UVM-based verification environments
  • System Verilog, UVM methodology
  • Constrained random verification
  • Regression management and debug
  • Scripting for automation

Nice-to-have

  • Mentorship and cross-functional influence
  • CI/CD, regression infrastructure
  • Low-power verification knowledge
  • Formal verification tools and methodologies

Key Requirements

  • 10+ years of experience in digital verification
  • BS or MS in Electrical and Computer Engineering
  • SoC level verification and signoff
  • Simulation and debug tools experience
  • Clock/reset domain crossing knowledge

Work Rights

Not specified

Tailored Resume

Cover Letter