Sr. Principal Ae - Verification Ip, Hpc Protocols

Cadence

San Jose, CA, US
Base: $143,500 to $266,500; bonus/equity: incentiv...
Pcie protocol expertise
Verification ip (vip) portfolio
System verilog and uvm
Bridge the gap between R&D and customers by providing technical expertise for Cadence's Verification IP portfolio

Job Summary

  • Bridge the gap between R&D and customers by providing technical expertise for Cadence's Verification IP portfolio.
  • Conduct product demonstrations, manage customer evaluations, and run benchmarks to prove tool value, deploying and integrating VIP into customer environments.
  • Benefits programs include paid vacation and holidays, 401(k) plan with employer match, employee stock purchase plan, and a variety of medical, dental, and vision plan options.

Matching Summary

Bridge the gap between R&D and customers by providing technical expertise for Cadence's Verification IP portfolio.

Salary

Base: $143,500 to $266,500; Bonus/Equity: Incentive compensation (bonus, equity); Benefits: Paid vacation, 401(k), ESPP, medical, dental, vision

Skills & Requirements

Must-have

  • PCIe protocol expertise
  • Verification IP (VIP) portfolio
  • System Verilog and UVM
  • Debugging pre-silicon verification failures
  • Customer technical support

Nice-to-have

  • Proactive problem solving
  • Continuous learning and innovation
  • Building customer trust and relationships
  • Mentoring junior engineers

Key Requirements

  • 8+ years of Design Verification Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • Requires approximately 10% travel on average

Work Rights

Not specified

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