Principal Verification Engineer

Altera Digital Health

New Delhi, India
Fully remote
10+ years asic or fpga verification experience
Expertise in systemverilog and uvm methodologies
Strong skills in python, perl, or tcl scripting
The role involves collaborating with architects to define comprehensive verification strategies for FPGA acceleration projects

Job Summary

  • The role involves collaborating with architects to define comprehensive verification strategies for FPGA acceleration projects.
  • Candidates will develop robust, reusable test environments using SystemVerilog and UVM to ensure design functionality.
  • The position requires executing simulation regressions and utilizing automation scripts to drive verification efficiency.

Matching Summary

The role involves collaborating with architects to define comprehensive verification strategies for FPGA acceleration projects.

Skills & Requirements

Must-have

  • 10+ years ASIC or FPGA verification experience
  • Expertise in SystemVerilog and UVM methodologies
  • Strong skills in Python, Perl, or TCL scripting

Nice-to-have

  • Familiarity with AMBA protocols like AXI and PCIe
  • Experience with formal verification methods
  • Knowledge of assertion-based verification (ABV)

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • 10+ years of experience in ASIC or FPGA design verification
  • Proficiency in HDL languages such as Verilog or VHDL

Work Rights

Not specified

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