Principal Ic Package Design Engineer

Cadence

Bangalore, India
On-site
Flip-chip package design
Ic-package-pcb co-design
Signal integrity (si)
Lead flip-chip package design with a strong focus on SI/PI and thermal constraints

Job Summary

  • Lead flip-chip package design with a strong focus on SI/PI and thermal constraints.
  • Drive IC–Package–PCB co-design, balancing performance, power, cost, technology, and thermal trade‑offs.
  • Collaborate closely with cross‑functional teams and customers to define and deliver optimal end‑to‑end solutions.

Matching Summary

Lead flip-chip package design with a strong focus on SI/PI and thermal constraints.

Skills & Requirements

Must-have

  • flip-chip package design
  • IC-Package-PCB co-design
  • signal integrity (SI)
  • power integrity (PI)
  • thermal optimization
  • 2D/3D EM simulations
  • S-parameters and RLGC models

Nice-to-have

  • work with diverse teams
  • continuous learning and development
  • innovative and impactful work

Key Requirements

  • 10+ years-15 years relevant experience
  • BE/BTech or MTech in Electrical / Electronics Engineering
  • Experience with Cadence Allegro tools (APD/SIP, PCB Editor)
  • Experience with modeling tools (Cadence Sigrity PowerSI, ExtractIM, Clarity 3D)
  • Experience with DRAM protocols (DDR4/5, GDDR6/7, HBM3/4, LPDDR5/6)

Work Rights

Not specified

Tailored Resume

Cover Letter