Rtl-gdsii, Sr Application Engineer

Cadence

Base: $84,000 to $156,000 (california); bonus/equi...
Not specified
Physical implementation at 7nm and below
Digital synthesis and place-and-route expertise
Static timing analysis and power optimization
Cadence is seeking a Sr Application Engineer to lead technical strategy and execution for advanced customer design projects, particularly in digital implementation at nodes of 3nm and below. The role involves collaborating with sales teams, mentoring junior engineers, and developing custom solutions using scripting languages

Job Summary

  • The role involves leading technical strategy for critical customer design projects at advanced nodes like 3nm and below.
  • Candidates will serve as primary consultants for synthesis, place & route, and timing signoff while leveraging AI in EDA.
  • The position offers competitive compensation including bonus, equity, and comprehensive benefits like a 401(k) match and stock purchase plan.

Matching Summary

Match Score: 85

Cadence is seeking a Sr Application Engineer to lead technical strategy and execution for advanced customer design projects, particularly in digital implementation at nodes of 3nm and below. The role involves collaborating with sales teams, mentoring junior engineers, and developing custom solutions using scripting languages.

Salary

Base: $84,000 to $156,000 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k) match, medical/dental/vision

Skills & Requirements

Must-have

  • Physical implementation at 7nm and below
  • Digital synthesis and place-and-route expertise
  • Static timing analysis and power optimization
  • Scripting proficiency in TCL, PERL, Python
  • Advanced node design convergence experience

Nice-to-have

  • Agentic-AI integration in EDA flows
  • Strong customer relationship building skills
  • Mentoring junior engineering teams
  • Experience with 3nm node technologies

Key Requirements

  • Bachelor's or Master's in Electrical/Computer Engineering
  • 2+ years hands-on experience in physical implementation
  • Multiple successful tapeouts at 7nm and below

Work Rights

Not specified

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