Asic Dft Dv Technical Leader

Cisco

San Jose, California, USA
Base: $168,800.00 to $241,200.00; bonus/equity: no...
Dft verification experience
Test planning and development
System verilog testbench development
You will work with Front-end RTL teams and backend physical design teams to understand chip architecture

Job Summary

  • You will work with Front-end RTL teams and backend physical design teams to understand chip architecture.
  • The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era.

Matching Summary

You will work with Front-end RTL teams and backend physical design teams to understand chip architecture.

Salary

Base: $168,800.00 to $241,200.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision insurance

Skills & Requirements

Must-have

  • DFT verification experience
  • Test planning and development
  • System Verilog testbench development

Nice-to-have

  • Knowledge of JTAG protocol
  • Experience with UVM
  • Collaboration with design teams

Key Requirements

  • Bachelor's or Master’s Degree in Electrical or Computer Engineering
  • At least 7 years of experience
  • Scripting skills in Tcl, Python/Perl

Work Rights

Not specified

Tailored Resume

Cover Letter