Ingénieur Vérification Asic R&d (f/h)

Atos

Les Clayes-sous-Bois, France
Hybrid (up to 60% remote work)
Uvm verification methodology
Constraint-random, coverage driven verification
Systemverilog/c++ verification environments
Atos is seeking an experienced ASIC Verification Engineer to join their R&D team in Les Clayes-sous-Bois, France. The role involves verifying complex ASIC designs using UVM methodologies and offers flexible work arrangements along with a competitive benefits package

Job Summary

  • The mission involves participating in the verification of a complex ASIC using Constraint-Random, Coverage Driven methodologies under the UVM standard.
  • Responsibilities include acquiring architectural knowledge, writing verification specifications and test plans, developing verification environments, and debugging simulation errors.
  • The company offers a competitive compensation package, hybrid work options, professional development, and a positive work environment.

Matching Summary

Match Score: 85

Atos is seeking an experienced ASIC Verification Engineer to join their R&D team in Les Clayes-sous-Bois, France. The role involves verifying complex ASIC designs using UVM methodologies and offers flexible work arrangements along with a competitive benefits package.

Skills & Requirements

Must-have

  • UVM verification methodology
  • Constraint-Random, Coverage Driven verification
  • SystemVerilog/C++ verification environments
  • SoC/ASIC/IP verification experience
  • Coverage analysis and improvement

Nice-to-have

  • Good interpersonal skills
  • Team player
  • Adaptable to interruptions
  • Professional French and English communication

Key Requirements

  • Experience in complex SoC/ASIC and IP verification
  • Experience with UVM methodology
  • SystemVerilog/C++ development for verification environments
  • Object-oriented programming mastery
  • Knowledge of simulation and coverage tools

Work Rights

Not specified

Tailored Resume

Cover Letter