15+ years technical experience in pre-silicon validation
Expertise in ovm/uvm and system verilog methodologies
Experience with constrained random verification techniques
The role involves leading a team responsible for the complete verification lifecycle of complex IPs and SoCs to ensure design specifications are met
Job Summary
The role involves leading a team responsible for the complete verification lifecycle of complex IPs and SoCs to ensure design specifications are met.
Candidates must integrate security-related testing into validation plans and collaborate with security teams to improve coverage through hackathon reviews.
The position requires driving results by inspiring team members, applying differentiated performance management, and maintaining accountability against milestone requirements.
Matching Summary
The role involves leading a team responsible for the complete verification lifecycle of complex IPs and SoCs to ensure design specifications are met.
Skills & Requirements
Must-have
15+ years technical experience in pre-silicon validation
Expertise in OVM/UVM and System Verilog methodologies
Experience with constrained random verification techniques
Proven track record managing verification teams
Strong scripting skills in TCL, PERL, or Python
Nice-to-have
Formal verification experience
Knowledge of Ethernet, PCIe, MACSEC, or IPSEC protocols
FPGA architecture or prototyping background
Experience driving continuous improvement in test suites
Background in SME or team management roles
Key Requirements
BS, MS, or PhD in Electrical or Computer Science Engineering
Minimum 15 years of technical experience in Pre Silicon Validation
Experience with emulation and system simulation models
Ability to root cause and debug issues in presilicon environments