Principal Engineer, Asic Verification - Ai/hpc Socs

Marvell

Base: cad 145,800 - 194,400 py; bonus/equity: not ...
12+ years experience in design engineering
5+ years hands-on verification on pcie/ddr/hbm
Systemverilog and uvm methodology expertise
This role involves leading the verification of complex custom SoCs for AI, HPC, and data center architectures at Marvell

Job Summary

  • This role involves leading the verification of complex custom SoCs for AI, HPC, and data center architectures at Marvell.
  • Candidates will develop advanced verification environments using SystemVerilog and UVM while collaborating with strategic customers and designers.
  • The position offers competitive compensation ranging from CAD 145,800 to 194,400 per annum along with a collaborative work culture.

Matching Summary

This role involves leading the verification of complex custom SoCs for AI, HPC, and data center architectures at Marvell.

Salary

Base: CAD 145,800 - 194,400 per annum; Bonus/Equity: Not specified; Benefits: Competitive compensation and great benefits

Skills & Requirements

Must-have

  • 12+ years experience in design engineering
  • 5+ years hands-on verification on PCIe/DDR/HBM
  • SystemVerilog and UVM methodology expertise
  • Develop functional verification environments
  • Lead geographically dispersed verification teams

Nice-to-have

  • Strong analytical and problem-solving skills
  • Excellent communication and collaboration abilities
  • Experience with Python or Perl scripting
  • Ability to multi-task in fast-paced environment

Key Requirements

  • Bachelor's degree with 12+ years experience
  • Master's or PhD with 10+ years experience
  • Eligibility for US export control access
  • Direct hands-on experience with block/subsystem verification

Work Rights

Must be eligible for US export-controlled information (US citizen, LPR, or protected individual)

Tailored Resume

Cover Letter