Job Summary

• Lead Analog IC Layout Engineer role within the ATE/DPS team, focusing on next-generation system-level solutions for electrification and semiconductor complexity.
• Key responsibilities include owning full-chip layout, serving as a technical resource and mentor, leading teams, and collaborating with cross-functional groups.
• The position offers a competitive salary range, performance-based bonus, and comprehensive benefits including medical, dental, vision, 401k, and paid time off.

Matching Summary

Salary

Base: $134,644 to $201,966; Bonus/Equity: discretionary performance-based bonus; Benefits: medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time

Skills & Requirements

Key Requirements

• 10+ years full-custom IC layout experience
• Degree in Electrical/Electronic Engineering or equivalent
• Proficiency with Cadence Virtuoso
• Expert knowledge of standard analog layout practices
• Strong planning, organizational, and documentation skills
• Excellent interpersonal and communication abilities
• Experience with high-voltage (HV) layout
• Background in precision analog electronics

Work Rights