Design Verification Engineer

Analog Devices, Inc.

Edinburgh, United Kingdom
Uvm methodology
Constrained random verification
Verilog and systemverilog
The Edinburgh team is seeking a Senior Design Verification Engineer to grow its talented group located in the city centre of the Scottish capital

Job Summary

  • The Edinburgh team is seeking a Senior Design Verification Engineer to grow its talented group located in the city centre of the Scottish capital.
  • The successful candidate will join a diverse team that is motivated, supportive, and eager to share its knowledge.
  • We allow our employees the freedom to explore new ideas and the autonomy to determine how to best achieve goals.

Matching Summary

The Edinburgh team is seeking a Senior Design Verification Engineer to grow its talented group located in the city centre of the Scottish capital.

Skills & Requirements

Must-have

  • UVM methodology
  • constrained random verification
  • Verilog and SystemVerilog
  • Python, Perl, Makefile scripting
  • IP and SoC level verification
  • functional coverage closure
  • code coverage closure

Nice-to-have

  • mixed-signal design experience
  • audio interface knowledge
  • power aware simulations
  • formal verification
  • DSP concepts

Key Requirements

  • 5-8 years of progressive experience
  • Electronic Engineering/Computer Engineering degree
  • experience developing UVM-based testbench
  • experience with AHB/AXI/APB/SWI3S protocols

Work Rights

Not specified

Tailored Resume

Cover Letter