Senior Soc Methodology Architect, Vlsi Physical Design

Nvidia Corporation

CA, United States
Base: 136,000 usd - 218,500 usd; bonus/equity: equ...
On-site
Floorplan development
Eda tool application
Placement and routing
Define and optimize top-level floorplan, including die size estimation, route planning and hierarchy definition and efficient partitioning

Job Summary

  • Define and optimize top-level floorplan, including die size estimation, route planning and hierarchy definition and efficient partitioning.
  • Drive internal tools and top-level floorplan methodologies for chip automation.
  • Collaborate with tool developers, architects, designers, and the top-level integration team to proactively identify and resolve issues.

Matching Summary

Define and optimize top-level floorplan, including die size estimation, route planning and hierarchy definition and efficient partitioning.

Salary

Base: 136,000 USD - 218,500 USD; Bonus/Equity: Equity; Benefits: Benefits

Skills & Requirements

Must-have

  • floorplan development
  • EDA tool application
  • placement and routing
  • chip automation methodologies
  • advanced process technologies

Nice-to-have

  • creativity and independence
  • intellectual freedom
  • top-tier AI hardware contributions

Key Requirements

  • BS, MS, in Electrical Engineering, Computer engineering, Computer Science or equivalent experience
  • 4+ years of relevant work experience
  • Verilog and synthesis understanding
  • Python, Perl and C/C++ programming language experience

Work Rights

Not specified

Tailored Resume

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