Senior Power And Performance Engineer - System Memory
NVIDIA
Base: $168,000 - $264,500 (level 4) or $196,000 - ...
Hybrid
8+ years memory subsystem architecture experience
System-level post-silicon bring-up and debug
Deep understanding of signal integrity and timing analysis
NVIDIA is seeking a Senior Power and Performance Engineer to join their Silicon Solutions Group, focusing on system memory features for various markets. Ideal candidates will have extensive experience in memory subsystem architecture and validation, coupled with strong problem-solving capabilities and teamwork skills
Job Summary
The role involves building roadmaps for memory system-level features to address low power, low noise, and perf/watt efficient product needs across notebook, desktop, and data center markets.
Candidates must possess validated hands-on lab experience with silicon bring-up, utilizing tools like oscilloscopes, multimeters, and logic analyzers for debugging and validation.
NVIDIA offers a competitive base salary range of $168,000 to $310,500 depending on level, along with equity and comprehensive benefits.
Matching Summary
Match Score: 85
NVIDIA is seeking a Senior Power and Performance Engineer to join their Silicon Solutions Group, focusing on system memory features for various markets. Ideal candidates will have extensive experience in memory subsystem architecture and validation, coupled with strong problem-solving capabilities and teamwork skills.
Salary
Base: $168,000 - $264,500 (Level 4) or $196,000 - $310,500 (Level 5); Bonus/Equity: Eligible for equity; Benefits: Comprehensive benefits package included
Skills & Requirements
Must-have
8+ years memory subsystem architecture experience
System-level post-silicon bring-up and debug
Deep understanding of signal integrity and timing analysis
Experience with control systems and boot/reset flows
Hands-on lab experience with oscilloscopes and logic analyzers
Nice-to-have
Proficiency in Python, Perl, C/C++ programming
Experience with adaptive control techniques
Strong problem-solving and teamwork skills
Knowledge of binning and pairing strategies
Key Requirements
BS or MS degree in EE/CE or equivalent experience
8+ years in memory subsystem architecture and validation
Strong fundamentals in digital/analog design and low power techniques