The role serves as the gatekeeper of IP Management, Methodology, and Quality to prevent late-stage integration breaks that delay tape-outs
Job Summary
The role serves as the gatekeeper of IP Management, Methodology, and Quality to prevent late-stage integration breaks that delay tape-outs.
Candidates will architect an AI-first ecosystem integrating agentic workflows to automate IP management and self-heal real issues.
The position requires deep expertise in verifying IP compliance for high-speed interfaces and performing independent LVS, DRC, and Antenna signoffs for 5nm/3nm nodes.
Matching Summary
The role serves as the gatekeeper of IP Management, Methodology, and Quality to prevent late-stage integration breaks that delay tape-outs.
Salary
Base: $175,000.00 – $230,000.00 USD; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
IP Lifecycle Management architecture
AI-driven automation workflows
Full EDA sign-off suite mastery
FinFET and GAA node expertise
Cross-view consistency auditing
Tcl and Python scripting
Nice-to-have
Detective mindset for root cause analysis
Experience with heterogeneous integration
Vendor management skills
Leadership of internal IP teams
Key Requirements
Mastery of PrimeTime, Calibre, and Fusion Compiler tools
Deep understanding of Liberty modeling and LEF/DEF formats
Expertise in Electromigration and ESD rules for advanced nodes