Celerocommunicationsinc is seeking a High-Speed CMOS PLL Design Engineer to contribute to the development of advanced High-Speed Interconnect Technology for next-generation AI applications. The role focuses on PLL architecture and design for optical transceivers, SerDes, and ADC/DAC systems, requiring a strong background in analog design and relevant experience in PLLs
Job Summary
Join a fast-growing start-up focused on high-speed interconnect technology.
Architect and design PLLs for next generation optical transceivers.
Conduct performance characterization using state-of-the-art lab equipment.
Matching Summary
Match Score: 85
Celerocommunicationsinc is seeking a High-Speed CMOS PLL Design Engineer to contribute to the development of advanced High-Speed Interconnect Technology for next-generation AI applications. The role focuses on PLL architecture and design for optical transceivers, SerDes, and ADC/DAC systems, requiring a strong background in analog design and relevant experience in PLLs.