Senior Asic Design Verification Engineer

Cisco UK

United Kingdom
Uvm based verification environment
Rtl design
Functional verification methodologies
Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation

Job Summary

  • Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
  • Your Impact Review micro-architecture specifications Supervise verification team members and provide professional guidance Implement Verification e nvironment UVM based.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.

Skills & Requirements

Must-have

  • UVM based verification environment
  • RTL design
  • functional verification methodologies
  • debug and root-cause analysis
  • post-silicon validation

Nice-to-have

  • MATLAB simulations
  • bit-exact modeling
  • mixed-signal systems
  • GLS experience

Key Requirements

  • 5+ years of experience
  • B.Sc./M.Sc. in Electrical Engineering
  • knowledge with UVM
  • functional verification methodologies

Work Rights

Not specified

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