As a DFX Architect, you will define the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world-class quality, minimize Test Cost (TCO), and accelerate Time-to-Market (TTM)
Job Summary
As a DFX Architect, you will define the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world-class quality, minimize Test Cost (TCO), and accelerate Time-to-Market (TTM).
Key responsibilities include defining DFX architectures for multi-die systems, driving adoption of advanced DFX features, developing strategies to reduce Test Data Volume and Test Application Time, and leading the definition of on-chip debug infrastructures.
This is a high-visibility leadership role requiring collaboration with Silicon Architecture, Physical Design, and Post-Silicon Manufacturing teams across global sites, with opportunities for mentorship and influencing EDA vendors.
Matching Summary
As a DFX Architect, you will define the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world-class quality, minimize Test Cost (TCO), and accelerate Time-to-Market (TTM).
Skills & Requirements
Must-have
DFX architectures for multi-die systems
Advanced DFT features adoption
Test Cost Optimization strategies
On-chip debug infrastructures definition
Cross-functional collaboration
EDA vendor influence
Nice-to-have
Technical beacon for engineering site
Balancing technical perfection with business constraints
Presenting complex technical roadmaps
Resolving mission-critical silicon issues
Key Requirements
10-12 years of hands-on DFT/DFD experience
4+ years in architectural or lead capacity
Familiar with semiconductor product lifecycle
Expertise in advanced DFT concepts
Experience with multi-die/chiplet technologies
Expert knowledge of silicon debug
Experience with ASIL-D functional safety standards