Mixed Signal Logic Verification Engineer

Intel

Bangalore, India
Hybrid
Uvm/system verilog testbench architecture
Mix signal ip verification strategy
Rtl debug and gate-level simulations
Develop, implement, and lead comprehensive verification plans for Complex Mix Signal IPs

Job Summary

  • Develop, implement, and lead comprehensive verification plans for Complex Mix Signal IPs.
  • Design and maintain advanced test benches, scoreboards, and checkers using System Verilog and UVM.
  • Perform RTL debug, gate-level simulations, and functional/code coverage analysis.

Matching Summary

Develop, implement, and lead comprehensive verification plans for Complex Mix Signal IPs.

Skills & Requirements

Must-have

  • UVM/System Verilog testbench architecture
  • Mix signal IP verification strategy
  • RTL debug and gate-level simulations
  • System Verilog and UVM expertise
  • Python, Perl, Tcl scripting skills

Nice-to-have

  • Mentoring junior engineers
  • Improving verification methodologies
  • Collaborating with architects
  • Formal verification methods

Key Requirements

  • 11-15 years of ASIC/SoC verification experience
  • Expert-level System Verilog, UVM, Verilog knowledge
  • Proficiency in JTAG/IJTAG/CRI/APB protocols
  • Experience with Synopsys VCS, Cadence Xcelium/JasperGold, Mentor Questa
  • B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI Engineering

Work Rights

Not specified

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