Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs
Job Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Participates in the definition of PCIe/CXL architecture and microarchitecture features of the block being designed.
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
Matching Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Skills & Requirements
Must-have
RTL design with Verilog and VHDL
logic simulations and design verification
PCIe/CXL architecture and microarchitecture
FPGA, custom IC or ASIC design
power, performance, area, and timing goals
Nice-to-have
highly motivated to learn
exceptional analytical skills
problem solving skills
promote innovation and teamwork
self motivated and ability to excel
Key Requirements
Bachelor degree in Electrical, Electronics, Computer Engineering or equivalent
10+ years of experience in RTL design
Experienced in FPGA, custom IC or ASIC design and verification