Physical Design Backend Sta Engineer

NVIDIA

Israel
Static timing analysis sta
Prime time tool usage
Sdc generation and review
The role involves performing advanced Static Timing Analysis at the chiplet and FC level for high-speed communication devices

Job Summary

  • The role involves performing advanced Static Timing Analysis at the chiplet and FC level for high-speed communication devices.
  • Engineers are responsible for running Prime Time, reviewing timing paths, and ensuring convergence throughout various project stages.
  • Candidates must have a B.Sc. in Electrical or Computer Engineering with 2-3 years of experience as an STA engineer.

Matching Summary

The role involves performing advanced Static Timing Analysis at the chiplet and FC level for high-speed communication devices.

Skills & Requirements

Must-have

  • Static Timing Analysis STA
  • Prime Time tool usage
  • SDC generation and review
  • Timing path debugging
  • Physical design convergence

Nice-to-have

  • Knowledge of PNR flows
  • Strong communication skills
  • Ability to adapt quickly
  • Innovative problem solving
  • Team collaboration experience

Key Requirements

  • B.Sc. in Electrical Engineering
  • 2-3 years STA experience
  • Strong adaptation ability

Work Rights

Not specified

Tailored Resume

Cover Letter