Soc Physical Design Timing Engineer

Intel

Bangalore, India
On-site
Sta and timing closure activities
Understanding of design, architecture and clocking
Interaction with fe/dft/verification teams
Responsible for STA and timing closure activities of Intel SoCs/Partitions

Job Summary

  • Responsible for STA and timing closure activities of Intel SoCs/Partitions.
  • Tasks include understanding design, architecture, clocking, and debugging timing issues.
  • Requires hands-on experience with industry-standard tools like Primetime and scripting skills in TCL/Perl/Shell.

Matching Summary

Responsible for STA and timing closure activities of Intel SoCs/Partitions.

Skills & Requirements

Must-have

  • STA and timing closure activities
  • Understanding of Design, Architecture and Clocking
  • Interaction with FE/DFT/Verification teams
  • Writing constraints
  • Synchronous - asynchronous paths
  • Clock domain crossing issues
  • Timing closure
  • Generating timing ECOs
  • Timing signoff
  • Debugging/troubleshooting timing issues
  • Primetime tool experience
  • TCL/Perl/Shell scripting skills

Nice-to-have

  • Strong initiative
  • Analytical/problem solving skills
  • Team working skills
  • Ability to multitask
  • Work within a diverse team
  • Self-motivated
  • Seek constant improvements
  • Driving new methodologies

Key Requirements

  • 10+ Years of relevant experience
  • Bachelor of Engineering or Master of Engineering in Electrical and/or Electronics Engineering
  • Skills in Physical Implementation and Timing Closure

Work Rights

Not specified

Tailored Resume

Cover Letter