The candidate will define the SoC level power delivery architecture and drive overall PDN convergence and signoff for next generation Xeon Server SoC designs
Job Summary
The candidate will define the SoC level power delivery architecture and drive overall PDN convergence and signoff for next generation Xeon Server SoC designs.
Responsibilities include validating IR drops using static IR, dynamic IR, Vless, and VCD checks for both die and package components.
The role requires collaboration with SOC and packaging teams to optimize bump assignments, RDL enablement, and package routing.
Matching Summary
The candidate will define the SoC level power delivery architecture and drive overall PDN convergence and signoff for next generation Xeon Server SoC designs.
Skills & Requirements
Must-have
Block level EM/IR analysis
Full chip level PDN analysis
Redhawk RHSC Voltus experience
Static IR Dynamic IR Vless checks
TCL Perl scripting skills
Nice-to-have
Good knowledge on Power Delivery
Effective global cross-functional communication
Innovus RDL and Bump Planning familiarity
Key Requirements
Bachelors or Masters in Electrical Engineering
At least 8+ years of experience in PDN analysis
Hands-on experience with Redhawk, RHSC, and Voltus