Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms, driving DFT requirements at architecture and RTL definition stages
Job Summary
Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms, driving DFT requirements at architecture and RTL definition stages.
Provide hands-on leadership for complex DFT implementations, including Scan Architecture, ATPG, Cell-Aware, Memory BIST and Repair, and support industrial test standards.
Mentor and guide Senior and Junior DFT engineers, set technical standards, and act as a go-to expert for complex DFT and testability issues across teams.
Matching Summary
Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms, driving DFT requirements at architecture and RTL definition stages.
Skills & Requirements
Must-have
end-to-end DFT architecture and strategy
DFT methodology evolution
Scan Architecture, ATPG, Cell-Aware
Memory BIST and Repair
IEEE 1149.1 (JTAG) and/or IEEE 1687 (IJTAG)
DFT sign-off quality
DFT-related timing constraints
Nice-to-have
post-silicon debug, yield ramp
industrial ATE platforms
low-power DFT
scripting and automation skills
influencing multi-site or global teams
Key Requirements
10+ years of industry experience in DFT design
Bachelor’s or Master’s degree in Electrical / Electronic Engineering or related field
Strong Verilog and/or SystemVerilog proficiency
Proven track record in driving AI or LLM to simplify or enhance DFT implementations