Ip Verification Engineer

Altera

Bengaluru, Karnataka, India
Systemverilog and uvm verification environments
5+ years asic or fpga design verification experience
Developing drivers, monitors, scoreboards, and checkers
The role involves collaborating with architects to define comprehensive verification strategies for FPGA acceleration projects

Job Summary

  • The role involves collaborating with architects to define comprehensive verification strategies for FPGA acceleration projects.
  • Candidates will develop robust, reusable verification environments using SystemVerilog and UVM methodologies.
  • The position requires executing simulation regressions and analyzing root causes to ensure verification completeness.

Matching Summary

The role involves collaborating with architects to define comprehensive verification strategies for FPGA acceleration projects.

Skills & Requirements

Must-have

  • SystemVerilog and UVM verification environments
  • 5+ years ASIC or FPGA design verification experience
  • Developing drivers, monitors, scoreboards, and checkers
  • Executing simulation regressions and debugging test failures
  • Defining functional and code coverage metrics

Nice-to-have

  • Familiarity with AMBA protocols like AXI and PCIe
  • Experience with Synopsys VCS or Cadence Xcelium tools
  • Strong scripting skills in Python or Perl
  • Participation in technical reviews of specifications

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering
  • 5+ years of experience in ASIC or FPGA design verification
  • Proficiency in Verilog, VHDL, and SystemVerilog

Work Rights

Not specified

Tailored Resume

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