Senior Design Verification Engineer- Mixed Signal Ip

Intel

Folsom, California, United States
Base: $164,470.00-311,890.00 usd; bonus/equity: st...
Hybrid
8+ years design verification experience
Systemverilog and ovm/uvm expertise
Mixed signal logic component verification
The role involves performing functional verification of mixed-signal logic components to ensure designs meet specification requirements

Job Summary

  • The role involves performing functional verification of mixed-signal logic components to ensure designs meet specification requirements.
  • Candidates will collaborate with digital and analog architects to improve verification of complex architectural features and meet performance goals.
  • Intel offers a competitive compensation package including stock bonuses, health benefits, and retirement programs.

Matching Summary

The role involves performing functional verification of mixed-signal logic components to ensure designs meet specification requirements.

Salary

Base: $164,470.00-311,890.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, vacation

Skills & Requirements

Must-have

  • 8+ years design verification experience
  • SystemVerilog and OVM/UVM expertise
  • Mixed signal logic component verification

Nice-to-have

  • Python or Perl scripting skills
  • DDRPHY validation knowledge
  • Formal Property Verification exposure

Key Requirements

  • BS degree in Computer Engineering/CS/EE with 8+ years experience
  • MS degree in related field with 6+ years experience
  • PhD in related field with 4+ years experience

Work Rights

Not specified

Tailored Resume

Cover Letter