Asic Engineering Technical Lead

Cisco UK

10+ years asic design verification experience
Uvm/system verilog proficiency
Test bench development from scratch
The role involves architecting block, cluster, and top-level DV environment infrastructure for Cisco's silicon products

Job Summary

  • The role involves architecting block, cluster, and top-level DV environment infrastructure for Cisco's silicon products.
  • Candidates will lead the ASIC bring-up process and collaborate closely with designers to debug issues during post-silicon integration.
  • This position offers full exposure to systems including silicon, hardware, software, telemetry, and security within a global innovation team.

Matching Summary

The role involves architecting block, cluster, and top-level DV environment infrastructure for Cisco's silicon products.

Skills & Requirements

Must-have

  • 10+ years ASIC design verification experience
  • UVM/System Verilog proficiency
  • Test bench development from scratch
  • Perl or Python scripting skills
  • Gate Level Simulation expertise

Nice-to-have

  • Experience with Forwarding logic or P4
  • Knowledge of emulation platforms like Veloce
  • Formal verification tools knowledge
  • Protocol experience in PCIe or Ethernet
  • Collaborative multi-functional team work

Key Requirements

  • Bachelor's or Master's degree in EE, CE, or related field
  • Minimum 10 years of related ASIC design verification experience
  • Proficiency in System Verilog constraints, structures, and classes

Work Rights

Not specified

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