K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit
Job Summary
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit.
The Senior DFT Engineer will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams.
With multiple launches planned through 2026 and 2027, K2 is focused on building bigger satellites to develop the solar system and become a Kardashev Type II civilization.
Matching Summary
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit.
Skills & Requirements
Must-have
RTL DFT insertion and scan chain optimization
ATPG tools and test pattern generation
Mixed-signal SoC test strategy development
Memory BIST and TAP controller insertion
Low-power DFT methodologies
DFT verification and silicon debug
Nice-to-have
MBIST/LBIST implementation and memory repair
Knowledge of IEEE 1149.x JTAG standards
Multi-voltage domain and power-aware DFT
Physical design impacts on DFT
Scripting for automation
Experience with high-speed SerDes or RF SoCs
Cross-functional and distributed team experience
Prior A0 silicon bring-up and yield ramp
Key Requirements
B.S. or M.S. in Electrical Engineering or related field
7+ years experience in DFT for complex SoCs
Strong debugging skills across RTL, gate-level, and silicon