The role involves defining ISP hardware architecture based on product features and performance requirements while estimating gate count and power consumption
Job Summary
The role involves defining ISP hardware architecture based on product features and performance requirements while estimating gate count and power consumption.
Candidates must lead, supervise, and mentor a team of RTL design engineers in close collaboration with algorithm and digital system teams.
Responsibilities include implementing ISP algorithms into hardware using Verilog, SystemVerilog, and High Level Synthesis tools like Catapult.
Matching Summary
Match Score: 85
The role involves defining ISP hardware architecture based on product features and performance requirements while estimating gate count and power consumption.
Skills & Requirements
Must-have
Verilog SystemVerilog SystemC HLS
CMOS Image Sensor ISP knowledge
Digital Design verification experience
Gate count and power optimization
Team leadership and mentoring
Nice-to-have
Strong time management skills
Adaptable to changes
Collaborative cross-functional communication
Results-oriented mindset
Key Requirements
Minimum MSEE or BSEE degree
7+ years digital design and verification experience