2026 Campus - Soc Backend Design Engineer

NXP USA INC.

Rtl synthesis to gds implementation
Floor planning and routing expertise
Sta timing convergence skills
The Digital Physical Design Engineer is responsible for the full physical implementation of IP, Subsystem, or IC design from RTL synthesis to GDS

Job Summary

  • The Digital Physical Design Engineer is responsible for the full physical implementation of IP, Subsystem, or IC design from RTL synthesis to GDS.
  • Key responsibilities include optimization through floor planning, routing, timing convergence, and ensuring compliance with all technology and reliability rules.
  • Candidates must possess strong script coding abilities in Perl, TCL, or Python within a Linux/Unix environment.

Matching Summary

The Digital Physical Design Engineer is responsible for the full physical implementation of IP, Subsystem, or IC design from RTL synthesis to GDS.

Skills & Requirements

Must-have

  • RTL synthesis to GDS implementation
  • Floor planning and routing expertise
  • STA timing convergence skills
  • DRC/LVS/Electromigration/IR drops verification
  • Perl/TCL/Python scripting in Linux

Nice-to-have

  • SoC backend design experience
  • Best physical design strategy definition
  • Excellent communication skills
  • Collaboration spirit
  • Problem solving related to physical design

Key Requirements

  • Master degree in microelectronics or electronic engineering
  • Relevant discipline major in computer science
  • Experience in SoC design preferred

Work Rights

Not specified

Tailored Resume

Cover Letter