The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs at a leader in programmable solutions
Job Summary
The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs at a leader in programmable solutions.
Candidates will apply various strategies and tools to write RTL code and optimize logic to meet strict IP release requirements.
The position requires involvement in creating design examples, hardware verification, and failure debugging for IP blocks.
Matching Summary
The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs at a leader in programmable solutions.
Skills & Requirements
Must-have
15+ years engineering experience
System Verilog and VCS simulator proficiency
RTL coding and logic optimization skills
C/C++/Perl/Python/TCL scripting expertise
IP block design and integration experience
Nice-to-have
FPGA design and programming background
RTL validation experience
Hardware brings up and debugging skills
Strong cross-team communication abilities
Key Requirements
Bachelor's or Master's degree in Electrical Engineering