Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Base: 196,000 usd - 310,500 usd (level 5); 232,000...
Timing sign-off flows
Custom macro design
Nanotime static timing analysis
Develop Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones using standard cells and custom designs

Job Summary

  • Develop Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones using standard cells and custom designs.
  • The timing analysis will include the application of variation and statistical parameters in timing-analysis.
  • With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers.

Matching Summary

Develop Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones using standard cells and custom designs.

Salary

Base: 196,000 USD - 310,500 USD (Level 5); 232,000 USD - 368,000 USD (Level 6); Equity/Benefits: Eligible

Skills & Requirements

Must-have

  • Timing sign-off flows
  • Custom macro design
  • NanoTime static timing analysis
  • Spice simulations
  • Advanced CMOS technologies
  • TCL and Python expertise

Nice-to-have

  • Optimize performance, yield, and reliability
  • Pushing frontiers of possibility
  • Amplify human inventiveness and intelligence

Key Requirements

  • MS or equivalent experience
  • 12+ years experience in ASIC Design and Timing
  • Hands-on experience in advanced CMOS technologies (5nm/3nm/2nm and beyond)
  • Familiarity with industry standard ASIC tools

Work Rights

Not specified

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