Senior Design Verification Engineer - Interconnect Ip
Invidia
Shanghai, China
Verification methodology and tools
System verilog programming skills
Python/perl scripting
The FBHUB Shanghai team focuses on memory subsystem IP design and verification, contributing to RTL development, verification infrastructure, coverage analysis, and performance validation
Job Summary
The FBHUB Shanghai team focuses on memory subsystem IP design and verification, contributing to RTL development, verification infrastructure, coverage analysis, and performance validation.
The role involves verification on FBHUB end-to-end functionality, performance and power optimization using various verification methodologies to improve efficiency.
The team collaborates closely with the Santa Clara FBHUB team to drive quality assurance and accelerate project execution across multiple GPU roadmap milestones.
Matching Summary
The FBHUB Shanghai team focuses on memory subsystem IP design and verification, contributing to RTL development, verification infrastructure, coverage analysis, and performance validation.
Skills & Requirements
Must-have
Verification methodology and tools
System Verilog programming skills
Python/Perl scripting
C/C++ programming
RTL based simulation and formal verification
Performance and power optimization
Verification infrastructure deployment
Nice-to-have
Complex testbench setup experience
AI coding tools experience
Good English communication skills
Automation and productivity improvement
Regression management
Coverage analysis
Key Requirements
4+ years work experience
Bachelor's or Master's degree in Electrical or Computer Engineering
Familiarity with verification methodology, tools, and flow